WiPLASH · Project

Wireless Links Inside Computer Chips Using Graphene Antennas for Faster Processing

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Imagine the wiring inside a computer chip is like a packed highway — the more lanes you add, the worse the traffic jams get. WiPLASH replaced some of those wires with tiny wireless links made from graphene, operating at terahertz frequencies. Think of it like adding a helicopter shuttle service above the gridlocked roads, so data can hop across the chip without fighting through congested wires. The goal was to make chips that can reconfigure their internal connections on the fly, targeting a 10X speed boost for demanding tasks like deep learning.

By the numbers

10X

Target improvement in execution speed and energy-delay product over state-of-the-art baseline

EUR 2,994,765

EU contribution for R&D

Consortium partners across 4 countries

Total project deliverables produced

Demo deliverables with experimental hardware demonstrations

The business problem

What needed solving

Modern computer chips pack dozens of specialized processing and memory units, but the wired connections between them are rigid, power-hungry, and don't scale well. As chips grow more complex for AI and high-performance computing, these internal wiring bottlenecks become the main limit on speed and energy efficiency. Companies designing next-generation processors need a fundamentally different way to move data inside chips.

The solution

What was built

The project built three key experimental prototypes: a full transceiver/antenna subsystem for sub-terahertz wireless communication, high-performance graphene fabricated at wafer scale with encapsulation, and the first co-integration of graphene antennas with custom SiGe transceivers. Together, these demonstrate the building blocks for wireless communication channels inside computer chips.

Audience

Who needs this

Semiconductor companies designing multi-core and heterogeneous processorsAI chip startups building dedicated deep learning acceleratorsHPC system designers facing interconnect bottlenecksGraphene and advanced materials manufacturers targeting electronics applicationsEDA tool companies developing next-generation chip design software

Business applications

Who can put this to work

Semiconductor & Chip Design

enterprise

Target: Fabless chip design companies and semiconductor foundries

If you are a chip design company struggling with interconnect bottlenecks in multi-core processors — this project developed miniaturized graphene antennas and sub-terahertz transceivers that create wireless communication channels inside chips. The co-integration of graphene antennas with SiGe transceivers was experimentally demonstrated, targeting a 10X improvement in execution speed and energy-delay product over current baselines.

AI Hardware & Edge Computing

enterprise

Target: Companies building dedicated AI accelerators and deep learning hardware

If you are an AI hardware company hitting performance walls with rigid on-chip interconnects for neural network workloads — this project built reconfigurable wireless chip-scale networks specifically optimized for biologically-plausible deep learning architectures. The wireless plane provides plasticity that lets the chip adapt its internal data paths to different AI model requirements, targeting 10X gains in speed and energy efficiency.

High-Performance Computing

enterprise

Target: Data center operators and HPC system integrators

If you are an HPC provider facing diminishing returns from scaling traditional wired interconnects in heterogeneous computing platforms — this project demonstrated on-chip wireless communication at the functional unit level using tunable graphene antennas in the terahertz band. With 7 partners across 4 countries validating the approach, the technology offers a path to more scalable and flexible processor architectures.

Frequently asked

Quick answers

What would it cost to license or adopt this wireless-on-chip technology?

The project operated with EUR 2,994,765 in EU funding across 7 partners, which gives a sense of the R&D investment required to reach this stage. Licensing terms would need to be negotiated directly with the consortium lead, Universitat Politecnica de Catalunya. Based on available project data, no commercial pricing model has been published.

Can this scale to industrial chip manufacturing?

The project demonstrated high-performance graphene at wafer scale including encapsulation, which is a key step toward manufacturing compatibility. However, this remains at the experimental demonstration stage — the deliverables focused on proving fabrication processes, not volume production. Scaling to commercial foundry processes would require additional development.

Who owns the IP and how can a company access it?

The intellectual property is held by the 7-partner consortium led by Universitat Politecnica de Catalunya in Spain. As an EU-funded RIA project, the IP terms follow Horizon 2020 grant agreement rules, meaning each partner owns the IP they generated. Licensing discussions would need to go through the coordinator.

How proven is the 10X performance claim?

The 10X improvement in execution speed and energy-delay product is the project's target objective, not a guaranteed commercial specification. The consortium produced experimental demonstrations of the key components — graphene antennas, transceivers, and their co-integration — which are the building blocks needed to validate that target.

What specific hardware was actually built and tested?

Three key demo deliverables were produced: a full transceiver/antenna subsystem ready for measurements, high-performance graphene at wafer scale with encapsulation, and the first co-integration of graphene antennas with full custom SiGe transceivers. These are experimental prototypes demonstrating feasibility of each component and their integration.

How long before this could appear in commercial products?

Based on available project data, the technology is at the experimental demonstration stage with component-level prototypes. Moving from lab demonstrations to commercial chip products typically requires several additional years of engineering, foundry partnerships, and reliability testing. The project ended in September 2023.

Consortium

Who built it

The WiPLASH consortium of 7 partners across 4 countries (Spain, Germany, Italy, Switzerland) is heavily academic, with 5 universities and only 1 industrial partner (14% industry ratio). This is typical for a FET Open project pushing fundamental technology boundaries. The single SME in the consortium suggests some commercial awareness, but the low industry ratio means this technology will need significant industry engagement to move from lab prototypes toward products. The coordinator, Universitat Politecnica de Catalunya, is a strong technical university but commercialization will require partnering with semiconductor companies not currently in the consortium.

UNIVERSITAT POLITECNICA DE CATALUNYACoordinator · ES
UNIVERSITAET SIEGENparticipant · DE
RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHENparticipant · DE
IBM RESEARCH GMBHparticipant · CH
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNEparticipant · CH
GESELLSCHAFT FUR ANGEWANDTE MIKRO UND OPTOELEKTRONIK MIT BESCHRANKTERHAFTUNG AMO GMBHparticipant · DE
ALMA MATER STUDIORUM - UNIVERSITA DI BOLOGNAparticipant · IT

How to reach the team

Universitat Politecnica de Catalunya, Spain — contact through university technology transfer office

Order a report on this consortium See UNIVERSITAT POLITECNICA DE CATALUNYA profile →

Next steps

Talk to the team behind this work.

Want to explore how wireless on-chip communication could impact your chip design roadmap? SciTransfer can arrange a technical briefing with the research team.

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