Imagine if your smart camera could recognize objects as well as a human but used a fraction of the battery. Instead of moving data back and forth between a brain and a memory bank, this tech blends them together using special materials that act like tiny switches. It's like replacing a bulky filing cabinet with a smart desk where the notes are written directly into the wood.
Current AI image recognition relies on power-hungry architectures that drain batteries and generate heat. There is a critical need for hardware that can process Vision Transformers (ViT) with significantly lower energy consumption than standard DRAM.
A compute-in-memory (CIM) demonstrator and a circuit-level simulator. These include 32x32 arrays using either epitaxial FTJ synaptic weights or 3D FeRAM.
If you are a device maker dealing with short battery life in AI cameras — this project developed a compute-in-memory unit that targets energy efficiency > 50 TOPS/Watt. This allows complex vision transformers to run locally without draining the battery.
If you are an ADAS provider dealing with the high power consumption of image recognition — this project developed ferroelectric oxide chips that expect a 30% energy improvement over DRAM. This reduces heat and power needs for real-time road analysis.
If you are a sensor company dealing with the need for high-accuracy AI at the edge — this project developed a CIM demonstrator targeting accuracy > 90%. This enables precise quality control on the factory floor without needing cloud connectivity.
Based on available project data, there is no specific pricing or cost-per-unit information provided.
The project is currently at TRL 4-5 and plans to use Chips JU pilot lines to ensure future manufacturability for volume production.
Based on available project data, specific licensing terms are not mentioned, though the project involves a consortium of 8 partners across 5 countries.
The FTJ-based components are designed to be monolithically integrated into the back-end of line (BEOL) of CMOS, while FeRAM is vertically stacked with CMOS.
The project period runs from 2024-10-01 to 2027-09-30.
The consortium is heavily research-oriented, consisting of 8 partners from 5 countries (AT, CH, DE, EL, KR). It is composed of 4 universities and 4 research organizations, with 0% industry participation. This indicates a high-risk, high-reward technical development phase focused on fundamental materials science and semiconductor architecture rather than immediate commercial productization.
Contact the National Center for Scientific Research 'Demokritos' in Greece.
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