Imagine if every brand of electronic device required its own unique language to work, forcing you to buy only one brand of gear. This project creates a universal language and a free blueprint for AI chips so different hardware can work together seamlessly. It's like moving from proprietary charging cables to a universal USB-C standard for AI processing power.
AI acceleration is currently dominated by a few large players using closed, proprietary hardware and software. This creates vendor lock-in, high costs, and prevents companies from customizing hardware for energy efficiency.
A multi-layered hardware-software stack including the SYCLOPS Edge Data Center (EDC) v1.0 and updated DPC++ and AdaptiveCPP compilers for RISC-V acceleration.
If you are a data center operator dealing with high energy costs and vendor lock-in for AI chips — this project developed a RISC-V and SYCL based stack that allows for green, application-specific processor customization to reduce power consumption.
If you are an edge computing provider dealing with the need to run heavy AI models on small, local devices — this project developed the SYCLOPS Edge Data Center (EDC) v1.0 to enable efficient AI acceleration at the edge.
If you are a security auditor dealing with 'black box' proprietary AI chips that cannot be verified — this project developed a standards-based, fully-open approach that enables trustworthy and verifiable hardware/software systems.
Based on available project data, no specific pricing is mentioned, but the project focuses on using free, open Instruction Set Architecture (RISC-V) to democratize acceleration and reduce monopoly costs.
Yes, the project specifically targets 'extreme analytics' and 'extremely large and diverse data' through a multi-layered hardware-software stack designed for both cloud and edge scaling.
The project is built on open standards, specifically RISC-V and SYCL, aiming for vendor-neutral interfaces and APIs to avoid proprietary lock-in.
It uses SYCL as a cross-architecture programming model, allowing it to work across different types of accelerators and hardware layers.
The project period is from 2023-01-01 to 2025-12-31, with a structured four-phase approach including design, prototyping, scaling, and validation.
The consortium is highly balanced for commercialization, featuring a 50% industry ratio with 4 industrial partners, 4 of whom are SMEs. With 8 partners across 7 countries, the group combines academic research with practical implementation, ensuring the open-standard AI tools are developed with market needs in mind.
Contact EURECOM GIE in France for technical specifications on the RISC-V platform.
Contact us to find a partner for implementing open-standard AI acceleration in your infrastructure.
