If you are a vehicle manufacturer dealing with the inability to reach Level 4/5 autonomy due to processing lags — this project developed the TYR chip that processes data from dozens of sensors with ultra-low latency to ensure 100% safety.
High-Efficiency AI Processors for Autonomous Driving and Cloud Data Centers
Imagine a brain for a car that can process a mountain of sensor data instantly without draining the battery. This project created a specialized chip that handles complex AI tasks much faster and with less power than standard processors. It is like replacing a general-purpose tool with a precision instrument designed specifically for high-speed AI thinking.
What needed solving
Current AI hardware is too energy-hungry and fragmented to support full Level 4/5 autonomous driving or efficient hyperscale AI inference. This creates a bottleneck where sensor data exceeds the real-time processing capabilities of existing semiconductors.
What was built
Two processor families: TYR for edge AI in vehicles and JOTUNN for datacenter inference, both based on a single-die 5nm architecture.
Who needs this
Who can put this to work
If you are a cloud provider dealing with massive energy costs for AI inference — this project developed the JOTUNN processor that maximizes throughput and energy efficiency for modern AI workloads.
If you are an IoT company dealing with fragmented and inefficient hardware for edge AI — this project developed a single-die architecture that combines high performance with low power consumption.
Quick answers
What is the cost or pricing model for these chips?
Based on available project data, specific pricing is not disclosed, but the project aims for low cost and high implementation efficiency.
Can this technology be scaled for industrial use?
Yes, the JOTUNN family is specifically optimized for hyperscale deployments in datacenters to maximize throughput.
What is the IP and licensing status?
The project utilizes a patented companion chip architecture for AI and digital signal processing.
How does this integrate into existing systems?
The chips are fabricated with 5nm technology and CoWoS packaging, making them ready for integration into next-generation automotive and cloud systems.
What is the development timeline?
The project period runs from 2023-07-01 to 2025-06-30, with RTL code currently frozen and final validations underway.
Who built it
The project is led by a single French SME, VSORA, which maintains 100% industry representation. This lean structure indicates a highly focused commercial drive, leveraging a single entity to manage the complex transition from architecture validation to 5nm chip fabrication.
Contact VSORA in France for technical specifications on TYR and JOTUNN chips.
Talk to the team behind this work.
Contact us to connect with VSORA for early adoption of 5nm AI hardware.