If you are a manufacturer dealing with short battery life in autonomous sensors — this project developed a hybrid spin-wave-CMOS system that reduces power consumption and optimizes performance per circuit area.
Ultra-Low Power Hybrid Computing Chips for Next-Generation IoT Devices
Imagine if computers could process information using waves, like ripples in a pond, instead of just pushing electricity through tiny wires. This method uses far less energy and doesn't heat up as much as current chips. The team is building a bridge that lets these wave-based systems talk to the standard electronics we already use today.
What needed solving
Current microelectronics are hitting a wall due to Moore's law, where increasing power density leads to overheating. This limits the performance of autonomous IoT devices that require high efficiency with ultra-low power.
What was built
A hybrid system comprising a YIG-based magnetic spin-wave chip, a CMOS Analog Periphery IC (APIC) for driving and readout, and a high-bandwidth RF interposer for packaging.
Who needs this
Who can put this to work
If you are a designer dealing with the physical limits of Moore's law and chip overheating — this project developed a roadmap to compete with CMOS in technology nodes below 1 nm.
If you are a provider dealing with the need for high-performance computing in tiny, power-constrained environments — this project developed a system using spin-wave majority gates to increase computing throughput.
Quick answers
What is the estimated cost or price of this technology?
Based on available project data, there is no specific pricing or unit cost mentioned; the project focuses on technical demonstration and TRL 5 development.
Can this be produced at an industrial scale?
The project uses TSMC for manufacturing the CMOS APIC, indicating a path toward industrial fabrication, though it is currently at a demonstrator stage.
How is the IP and licensing handled?
Based on available project data, specific licensing terms are not provided, but the project involves a consortium of 7 partners across 6 countries.
How does this integrate with existing hardware?
It uses a large bandwidth RF interposer to co-integrate the spin-wave circuit and a mixed-signal CMOS chip into a single package.
What is the development timeline?
The project runs from 2022-12-01 to 2026-11-30, with second-generation chips taped out in early 2025.
Who built it
The consortium is well-balanced for a deep-tech project, consisting of 7 partners from 6 countries. With an industry ratio of 29% (including 2 industrial partners and 1 SME), the project bridges the gap between academic research (2 universities, 3 research centers) and commercial manufacturing, evidenced by the use of TSMC for chip fabrication.
Contact INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM (imec) in Belgium.
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