If you are an encryption service provider dealing with vulnerabilities in pseudo-random number generators — this project developed the RPU that provides provably unpredictable randomness to secure data storage and communication.
Quantum Hardware Accelerator for Ultra-Secure Encryption and High-Performance Random Computing
Imagine your computer's 'random' numbers are actually like a predictable pattern in a book; a clever hacker can guess the next page. This technology uses the weird laws of quantum physics to create truly unpredictable numbers that no one can guess. It's like replacing a predictable dice roll with a cosmic event that is genuinely random every single time.
What needed solving
Current CPUs and GPUs use predictable pseudo-random numbers, creating security holes in encryption and inefficiencies in high-performance computing. This leads to higher operational costs and vulnerability to cyber attacks.
What was built
A PCIe-based hardware accelerator (RPU) integrating a Quantum Random Number Generator chip and FPGA logic, including a PCIe driver and SDK.
Who needs this
Who can put this to work
If you are a quantitative hedge fund dealing with inefficient Monte Carlo simulations — this project developed a hardware accelerator that optimizes randomized workloads to reduce OPEX and CAPEX costs.
If you are a 5G infrastructure operator dealing with the threat of post-quantum cryptography attacks — this project developed a PCIe-based prototype delivering 1 Gbps of quantum entropy to secure high-throughput data transfers.
Quick answers
What is the cost or pricing model for the RPU?
Based on available project data, specific unit pricing is not disclosed, but the company forecasts over 170 M in turnover from RPU sales between 2024-2028.
Can this be scaled for industrial use?
Yes, the project is developing a next-generation Photonic Integrated Chip (PIC) specifically to improve efficiency and scalability for the RPU product line.
What is the IP status and licensing situation?
The technology is protected by 14 patent families, which have either been filed or granted.
How does this integrate into existing server hardware?
The RPU is designed as a PCIe-based card with a Gen3 x4 interface, supported by a dedicated PCIe driver and SDK for host system interaction.
What is the timeline for commercial availability?
A TRL 7 prototype was presented in December 2022, and the project period runs from 2024-03-01 to 2026-02-28.
Who built it
The project is led by a single Spanish SME, Quside Technologies SL. This lean structure indicates a high level of internal control over the IP and a direct path to commercialization, as the company is a spin-off from the Institute of Photonics Sciences and holds 100% of the industry ratio in the consortium.
Contact QUSIDE TECHNOLOGIES SL via their corporate office in Spain.
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