Imagine if satellites had the brainpower of a modern smartphone instead of an old calculator. This project creates a way to build complex software for space that is guaranteed to work without crashing, using a 'blueprint' method that writes the code automatically. It also builds a specialized hardware chip that can handle AI tasks while keeping different programs safely separated from each other.
Current satellite computers are too weak to run AI, and the software development process is too slow and risky for complex modern systems. This leads to higher costs and lower competitiveness for space agencies.
A hardware prototype on an AMD VCU118 FPGA featuring a RISC-V processor with an AI accelerator, and a model-based design toolchain for automatic, correct-by-construction code generation.
If you are a satellite manufacturer dealing with the need to process AI data in orbit rather than sending it to Earth — this project developed a hardware prototype on an FPGA that enables high-performance computing. This allows for the execution of complex algorithms while maintaining strict safety standards.
If you are a secure communications provider dealing with the risk of software errors crashing a whole system — this project developed a hypervisor-based software stack. This ensures that different software units are isolated, so a failure in one does not affect others.
If you are a chip designer dealing with the challenge of creating space-qualified processors — this project developed an enhanced NOEL-V RISC-V processor with a SPARROW SIMD AI Accelerator. This provides a blueprint for high-performance, open-architecture hardware for extreme environments.
Based on available project data, specific pricing or implementation costs are not provided.
The project demonstrated effectiveness using space-related use cases and a hardware prototype on an FPGA, suggesting a path toward industrial scaling for institutional space programs.
The project utilizes the open source version of FrontGrade Gaisler's NOEL-V RISC-V processor, though specific licensing for the project's enhancements is not detailed.
The software layer is designed to guarantee dependability in compliance with ECSS standards through the use of hypervisors.
The project period ended on 2024-12-31, having completed the prototype and demonstration phases.
The consortium is heavily weighted toward industrial application, with a 60% industry ratio consisting of 3 companies and 2 research centers. The presence of an SME technology integrator (FEN) and a major end-user from the space sector (OHB) indicates that the project was designed for direct commercial and operational utility rather than pure academic research.
Contact the Barcelona Supercomputing Center (BSC) regarding the METASAT toolchain.
Contact us to find partners for implementing RISC-V AI accelerators in space hardware.
