If you are a cloud provider dealing with rising energy costs and waste heat management — this project developed magnonic neural networks that transport data without electrical leads. This reduces the carbon footprint of large-scale AI processing.
Ultra-Low Energy Computing Hardware Using Spin-Wave Neural Networks
Imagine if computers could process information using ripples in a magnet instead of electricity flowing through wires. This removes the heat and energy waste that slows down today's chips. It's like switching from a heavy power cable to a wireless wave to move data, making AI hardware much greener.
What needed solving
Computing power is currently limited by power loss (dissipation), which leads to high energy costs, overheating chips, and a large carbon footprint for ICT infrastructure.
What was built
Experimental magnonic neurons and neural networks, including magnonic field programmable gate arrays (mFPGAs), reservoir computers (mRCs), and recurrent neural networks (mRNNs).
Who needs this
Who can put this to work
If you are a chip designer dealing with the power loss bottleneck in ICT — this project developed magnonic field programmable gate arrays (mFPGAs). These components offer a green path forward for high-tech data processing and storage.
If you are a hardware developer dealing with limited battery life for on-device AI — this project developed magnonic reservoir computers and recurrent neural networks. These use low-energy magnetic excitations to solve data-driven problems.
Quick answers
What is the estimated cost or price of these components?
Based on available project data, there is no specific pricing or cost-per-unit information provided; the focus is on reducing energy costs for end consumers.
Can this be produced at an industrial scale?
The project explores compatibility with MRAM, which is already compatible with CMOS, suggesting a path toward industrial integration, though current work is at the research stage.
How is the IP and licensing handled?
The project aims to disseminate developed and appropriately protected designs, processes, and technologies to European and international companies.
How does this integrate with current hardware?
The technology is designed to be compatible with CMOS through MRAM and other spintronics technology paradigms.
What is the timeline for commercial availability?
The project period runs from 2022-09-01 to 2026-02-28, indicating it is currently in the research and development phase.
Who built it
The consortium consists of 6 partners across 5 countries, showing a strong academic lean with 4 universities and 1 research institute. However, there is a strategic industrial presence with 1 industry partner and 2 SMEs, resulting in a 17% industry ratio, which indicates the project is primarily focused on fundamental technology breakthroughs with a bridge to commercial application.
Contact Aalto Korkeakoulusaatio SR in Finland
Talk to the team behind this work.
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