IONS4SET · Project

Ultra-Low-Power Transistor Technology for Next-Generation IoT Chips

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Imagine billions of tiny sensors and gadgets all talking to each other — that's the Internet of Things. The problem is they all need power, and regular chips are energy hogs. This project figured out how to build a new kind of transistor using silicon dots so small (about 2 nanometers) that they move just one electron at a time, slashing energy use dramatically. They invented a self-assembly trick where ion beams and heat coax these tiny dots into exactly the right position — something traditional chip-making methods simply can't do at this scale.

By the numbers

~2 nm

Silicon nanodot diameter achieved through self-assembly

1–3 nm

Feature sizes targeted for room-temperature SET operation

20–50 nm

Pillar dimensions demonstrated on SiO2 island layers

EUR 3,999,205

Total EU contribution to the project

6 partners, 5 countries

Research consortium size and geographic spread

Total project deliverables produced

The business problem

What needed solving

The Internet of Things demands chips that consume almost no power — billions of always-on sensors and devices need to run on tiny batteries for years. Current CMOS transistors waste too much energy at the extreme miniaturization scales IoT requires. There is no reliable, mass-manufacturable process for building room-temperature single-electron transistors that could solve this power problem.

The solution

What was built

The project developed a self-assembly fabrication process using ion irradiation to create precisely positioned silicon nanodots (~2 nm) inside narrow pillars, demonstrated with first pillar structures at 20-50 nm on SiO2 layers. The goal was a vertical gate-all-around nanowire single-electron transistor (GAA-SET) compatible with existing CMOS manufacturing, with 26 deliverables produced across the project lifetime.

Audience

Who needs this

Semiconductor foundries exploring sub-5nm process technologiesIoT chipmakers needing ultra-low-power processor architecturesSemiconductor equipment manufacturers (ion beam and lithography tools)Edge computing hardware companies building battery-powered AI devicesResearch-intensive electronics companies scouting next-generation transistor designs

Business applications

Who can put this to work

Semiconductor Manufacturing

enterprise

Target: Chip fabrication companies and foundries developing next-generation process nodes

If you are a semiconductor foundry pushing beyond current lithography limits — this project developed a self-assembly fabrication process that creates precisely positioned 2 nm silicon dots with tunneling distances of about 2 nm. This could enable hybrid SET-CMOS chip architectures that dramatically cut power consumption while maintaining performance, opening a new product line for ultra-low-power IoT processors.

IoT Hardware & Edge Computing

any

Target: IoT device makers struggling with battery life and power budgets

If you are an IoT hardware company dealing with devices that drain batteries too fast — this project built the foundation for single-electron transistors that operate at room temperature using feature sizes of 1 to 3 nm. Hybrid SET-CMOS chips based on this research could extend device battery life by orders of magnitude, a critical advantage when you have thousands of deployed sensors.

Semiconductor Equipment & Materials

mid-size

Target: Companies supplying ion beam, lithography, or thin-film deposition equipment

If you are a semiconductor equipment supplier looking for the next growth market — this project demonstrated that ion irradiation through thin silicon pillars with embedded SiO2 layers triggers controlled nanodot self-assembly at sub-5 nm scales. This fabrication method could create demand for new ion beam tools and pillar fabrication equipment tailored to SET-CMOS production lines.

Frequently asked

Quick answers

What would it cost to license or adopt this technology?

The project was publicly funded under Horizon 2020 with EUR 3,999,205 in EU contribution and carried out by 6 research organizations with zero industrial partners. Licensing terms would need to be negotiated directly with the coordinator (Helmholtz-Zentrum Dresden-Rossendorf). As a Research and Innovation Action, IP is typically held by the consortium partners.

Can this scale to industrial chip production?

The core fabrication process — ion irradiation plus thermal self-assembly — was demonstrated on silicon pillars of 20 to 50 nm. Scaling to full wafer-level manufacturing would require significant further development, as the project focused on proving the physical process works, not on production-line integration. No industrial manufacturing partner was involved in the consortium.

What is the IP situation and how can I access the technology?

With 26 total deliverables produced across 6 research-only partners, substantial IP likely exists in the form of patents and know-how around the self-assembly process. The consortium included no industrial partners, so IP is held entirely by research institutions across 5 countries (DE, ES, FI, FR, IT). Contact the coordinator for licensing discussions.

How far is this from being used in real products?

This is early-stage research. The project aimed to 'pave the way' for fabrication of room-temperature single-electron transistors. Demo deliverables describe 'first pillars' on SiO2 layers, indicating proof-of-concept stage. Multiple engineering steps remain before this reaches commercial chip production.

Does this work at room temperature or only in a lab?

A key goal of IONS4SET was specifically room temperature operation. Single-electron transistors traditionally require cryogenic cooling, but by achieving dot diameters below 5 nm (targeting approximately 2 nm), the project aimed to overcome this barrier. Based on available project data, initial demonstrations of the fabrication process were achieved.

What standards or regulations apply?

Semiconductor manufacturing is governed by industry standards from organizations like SEMI and JEDEC. Any hybrid SET-CMOS chips would need to meet standard reliability and performance qualifications. The CMOS-compatible fabrication approach was a deliberate design choice to align with existing manufacturing standards.

Consortium

Who built it

The IONS4SET consortium is entirely research-driven: 5 research organizations and 1 university across Germany, Spain, Finland, France, and Italy, with zero industrial partners and zero SMEs. The coordinator, Helmholtz-Zentrum Dresden-Rossendorf, is a major German research center with strong expertise in ion beam physics. While the EUR 3,999,205 budget and 26 deliverables show serious scientific output, the complete absence of industry partners means no company has yet validated or co-developed this technology for manufacturing. Any business looking to adopt this would be entering at the ground floor — high risk, but also first-mover opportunity if the fabrication process proves scalable.

HELMHOLTZ-ZENTRUM DRESDEN-ROSSENDORF EVCoordinator · DE
HELSINGIN YLIOPISTOparticipant · FI
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESparticipant · FR
AGENCIA ESTATAL CONSEJO SUPERIOR DE INVESTIGACIONES CIENTIFICASparticipant · ES
CONSIGLIO NAZIONALE DELLE RICERCHEparticipant · IT

How to reach the team

Helmholtz-Zentrum Dresden-Rossendorf (Germany) — contact through their technology transfer office for licensing and collaboration inquiries

Order a report on this consortium See HELMHOLTZ-ZENTRUM DRESDEN-ROSSENDORF EV profile →

Next steps

Talk to the team behind this work.

Want to explore how ultra-low-power SET-CMOS technology could fit your IoT product roadmap? SciTransfer can connect you directly with the research team and help evaluate licensing options.

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