If you are a chip design house dealing with 3nm designs that require 400 CPU-months for verification — this project developed HyperPV that uses GPU acceleration to slash verification time and maximize production.
GPU-Accelerated Software to Speed Up Semiconductor Chip Design Verification
Imagine checking a giant city map for tiny errors before building it; usually, this takes weeks using a few slow computers. This technology switches the heavy lifting to powerful graphics cards, which can handle thousands of tasks at once. It turns a process that takes months of computing time into something much faster and cheaper.
What needed solving
Chip verification is a bottleneck that takes weeks of computing time and consumes massive energy. Current CPU-based tools cannot keep up with the exponential growth of design rules in 7nm and 3nm chips.
What was built
A GPU-powered verification system consisting of HyperDRC (a high-performance checking engine) and HyperCloud (a SaaS delivery platform).
Who needs this
Who can put this to work
If you are an IC producer dealing with the risk of huge losses from undetected design errors — this project developed HyperDRC that accelerates the checking of over 20k rules for 7nm processes.
If you are an EDA software provider dealing with energy-inefficient CPU-based tools — this project developed a SaaS cloud platform that provides high-performance computing for physical verification.
Quick answers
How does this reduce the cost of chip design?
It replaces expensive, energy-inefficient CPU farms (which can require 300+ CPUs) with GPU-powered acceleration, reducing the economic burden and energy consumption.
Can this handle industrial-scale chip complexity?
Yes, it is designed for modern complexities such as 7nm processes requiring over 20k rules and 100k operations.
What is the IP or licensing model?
Based on available project data, the solution is delivered as a SaaS cloud platform and includes a proprietary computational geometry library.
How does it integrate into the current design workflow?
It acts as a Physical Verification (PV) engine, specifically for Design Rule Checking (DRC), accessible via a cloud platform.
What is the timeline for deployment?
The project period runs from 2023-01-02 to 2025-07-01.
Who built it
The project is led by a single Romanian SME, AMSIMCEL SRL, with a 100% industry ratio. This lean structure suggests a highly focused commercial drive, utilizing a EUR 2,500,000 EU contribution to move from development to market.
Contact AMSIMCEL SRL in Romania for licensing and SaaS access.
Talk to the team behind this work.
Contact us to connect with the HyperPV team for early adoption of GPU-accelerated EDA tools.