If you are a data center operator dealing with processor bottlenecks and high energy costs — this project developed UHS SRAM that can reach 2-3x higher speed and reduce energy consumption by 30%. This allows for unprecedented cloud-computing performance.
Ultra-Fast Memory Chips to Boost Cloud Computing and IoT Battery Life
Imagine the memory in your device is like a narrow hallway that slows down the rest of the computer. This project built a wider, faster hallway that lets data move much quicker. It also acts like a smart light switch, turning off power when not in use so your battery lasts way longer.
What needed solving
SRAM acts as a bottleneck in electronics, causing excessive power drain in idle IoT devices and limiting the processing speed of data centers and telecom infrastructure.
What was built
A UHS SRAM compiler and a High-Speed Turbo (HSTB) memory product line, both validated via a fabricated FinFET test chip.
Who needs this
Who can put this to work
If you are a wearable device manufacturer dealing with short battery life due to idle power drain — this project developed SRAM that reduces energy consumption by 70-90% when the device is idle.
If you are a 5G infrastructure provider dealing with data processing limits in your hardware — this project developed a High-Speed Turbo (HSTB) memory line optimized for large, high-speed sequential data access.
Quick answers
What is the pricing or cost model for this technology?
Xenergic provides customers with SRAM design IP tailored to their requirements and generates revenue through royalties on the resulting sales.
Is this technology ready for industrial scale?
Yes, the project involved the design and fabrication of a test chip using advanced FinFET technology to validate performance under real-world conditions for wide-scale adoption.
How is the Intellectual Property (IP) handled?
The company licenses its Ultra-High-Speed (UHS) SRAM IP to semiconductor companies to be integrated into their system-on-chip (SoC) designs.
How does this integrate into existing hardware?
The technology is delivered as a compiler and IP blocks designed for advanced FinFET process nodes, allowing it to be embedded directly into SoC designs.
What is the timeline for market availability?
Based on available project data, the project ran from 2022 to 2024 to make these memories market-ready through silicon validation.
Who built it
The project was executed by a single partner, XENERGIC AB, a Swedish SME. This lean structure indicates a highly focused internal development cycle where the company maintains 100% control over the IP and industrial implementation.
Contact XENERGIC AB in Sweden for IP licensing inquiries
Talk to the team behind this work.
Contact us to find integration partners for high-speed SRAM IP.