If you are a network equipment provider dealing with signal loss and power inefficiency in 6G hardware — this project developed RF components and 7nm FD-SOI technology that improves chip performance and efficiency.
European Advanced Semiconductor Pilot Line for High-Performance 7nm and 10nm Chips
Imagine a high-tech kitchen where engineers can bake incredibly small and efficient computer chips. Instead of just one recipe, they are creating a versatile system that lets them stack components like LEGOs and add special memory and power tools. This allows companies to build smarter, faster electronics without needing to rely on factories outside of Europe.
What needed solving
European companies lack domestic access to advanced 7nm and 10nm semiconductor manufacturing, forcing reliance on foreign foundries and slowing down the development of high-efficiency chips.
What was built
A semiconductor pilot line featuring 7nm/10nm FD-SOI technology, 3D stacking, and embedded non-volatile memory. It includes a network of nearly 200 clean room tools across four European sites.
Who needs this
Who can put this to work
If you are an automotive chip designer dealing with bulky power components — this project developed magnetic inductances for PMIC that allow for smaller, more efficient power management integrated circuits.
If you are an AI hardware startup dealing with high energy consumption in edge devices — this project developed 10nm and 7nm FD-SOI nodes with embedded non-volatile memory that reduces power waste.
Quick answers
What is the cost or pricing for using the pilot line?
Based on available project data, specific pricing is not listed, but access is provided through reactive feasibility evaluations and annual open calls.
Is this technology available at an industrial scale?
The project establishes a pilot line integrating close to 200 clean room tools at 300mm, bridging the gap between research and full industrial production.
How is intellectual property and licensing handled?
The pilot line is designed to support the generation of intellectual property to maintain European technological leadership.
What is the timeline for accessing these technologies?
The project period runs from 2023-12-01 to 2028-12-31, indicating a multi-year development and access window.
How can a company integrate these chips into their products?
Forty industry leaders, including Bosch and STMicroelectronics, have already pledged to leverage the capacity for technology evaluation and product integration.
Who built it
The consortium is heavily weighted toward research and technical expertise, consisting of 11 partners from 8 countries. While there are 0 commercial companies in the core consortium, the operational strength is high with 4 dedicated Hosting Sites (CEA-Leti, Tyndall, VTT, SAL) and 6 RTOs/Universities. This structure suggests a focus on high-end technical development and prototyping rather than immediate commercial sales, though the 40 external industry supporters provide a clear path to market.
Contact CEA-Leti in France for access to the pilot line open calls.
Talk to the team behind this work.
Contact us to identify which 7nm or 10nm FD-SOI applications fit your product roadmap.