If you are a data centre operator dealing with skyrocketing electricity bills and CPU bottlenecks — this project developed Processing-In-Memory (PIM) technology that makes servers up to 20x faster and 12x more efficient.
High-Performance Memory Chips to Slash Data Centre Energy and Processing Costs
Imagine if your computer's brain had to walk across town every time it needed a piece of information from its filing cabinet; that's how current servers work. This technology puts the brain directly inside the filing cabinet, so the work happens where the data lives. It stops the constant, energy-hungry commuting of data, making everything run much faster and cooler.
What needed solving
Data centres waste 80% of their compute energy simply moving data between memory and the CPU. This creates a structural bottleneck that slows down AI and Big Data processing while driving up electricity costs.
What was built
A semiconductor-based Processing-In-Memory (PIM) chip and associated control software, including a module that fits into standard server memory slots.
Who needs this
Who can put this to work
If you are an AI provider dealing with slow processing speeds for Big Data — this project developed PIM modules that fit into standard memory slots and are 10x cheaper than conventional memory setups.
If you are a security firm dealing with data leakage during transfer between CPU and memory — this project developed a new security scheme to make PIM elements secure enclaves.
Quick answers
How does this affect the total cost of ownership?
PIM equipped servers have proven to be 10x cheaper for Big Data and AI applications compared to those using conventional memory.
Can this be deployed at an industrial scale?
Yes, the modules are designed to fit into standardized server memory slots and the team has worked with prime server partners like Intel, QCT, and Supermicro for integration.
What is the IP or licensing status?
Based on available project data, the technology is developed by SAS UPMEM, but specific licensing terms are not provided.
How difficult is the hardware integration?
Integration is simplified because the technology leverages existing industry protocols and fits into standard server memory slots.
What is the timeline for deployment?
The project period ran from 2022-03-01 to 2024-02-29, indicating the design and integration work is now complete.
Who built it
The project is led by a single French SME, SAS UPMEM, which maintains 100% industry control. This lean structure allowed for direct collaboration with major hardware giants like Intel, QCT, and Supermicro, ensuring the technology is compatible with global server standards rather than remaining a theoretical academic exercise.
Contact SAS UPMEM in France for PIM module integration
Talk to the team behind this work.
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