If you are an IoT device manufacturer dealing with high development costs for custom hardware — this project developed a design solution and library that makes SoC design more affordable for SMEs and start-ups.
Automated Chip Design Software to Reduce Semiconductor Development Costs and Time-to-Market
Imagine building a complex electronic brain for a device like playing with advanced Lego sets instead of carving every single piece from scratch. This tool provides a library of pre-made parts and a smart assembly program to put them together. It lets people create powerful chips without needing to be world-class experts in semiconductor physics.
What needed solving
Chip design is currently too slow, expensive, and requires rare expertise, leaving Europe dependent on non-EU suppliers and struggling with a qualified workforce shortage.
What was built
An extended SoC Compiler software platform and a library of pre-designed SoC subsystems for Arm and RISC-V architectures.
Who needs this
Who can put this to work
If you are a component supplier dealing with long delivery times and chip shortages — this project developed an automated design platform that lowers time-to-market for high-performance electronic components.
If you are a hardware startup dealing with the complexity of open-source architecture implementation — this project developed a software solution specifically targeting RISC-V SoCs to increase designer productivity.
Quick answers
How does this affect the cost of chip design?
The solution is designed to make the SoC design process more affordable, specifically targeting a lower cost for the creation of complex and high-performance electronic components.
Can this be scaled for industrial production?
Yes, the project aims to support the EU Chips Act goal of doubling Europe's share in global chip production from 10% to 20% by 2030.
What is the IP or licensing status of the architecture?
The project specifically targets Arm-based and RISC-V architectures, with RISC-V being highlighted as a strategic open-source technology.
How does this integrate with existing design workflows?
It integrates via the SoC Compiler software platform and a pre-design library of subsystems to automate the design process.
What is the expected timeline for impact?
The project runs from 2024-04-01 to 2026-09-30, aligning with the broader 2030 goals of the EU Chips Act.
Who built it
The project is led by a single French SME, Defacto Technologies, which holds 100% of the industry ratio. This lean structure suggests a highly focused commercial drive, leveraging 20 years of internal R&D and existing relationships with the world's top 20 semiconductor firms rather than academic research.
Contact Defacto Technologies in France regarding the SoC Compiler platform.
Talk to the team behind this work.
Contact us to explore licensing or partnership opportunities with Defacto Technologies.