Imagine having a hearing test that says you're fine, but you still can't understand a conversation in a crowded restaurant. This happens because the connections between the ear and brain are damaged, even if the ear itself works. This project creates a portable brain-scan device to find this 'hidden' loss and a smart chip that cleans up sound specifically for that person's brain.
Standard hearing tests cannot detect 'hidden hearing loss' (cochlear synaptopathy), leaving a huge portion of the population unable to communicate in noisy environments despite 'normal' test results.
A portable encephalogram-based diagnostic device (CochSyn) and a real-time neural-network sound processing algorithm (CoNNear) implemented on FPGA hardware.
If you are a clinic owner dealing with patients who fail standard audiograms but still struggle with speech in noise — this project developed the CochSyn test device that quantifies hidden hearing loss. This allows for early diagnosis and personalized treatment plans.
If you are a hardware developer dealing with generic noise-canceling that doesn't help with speech clarity — this project developed the CoNNear algorithm. This neural-network architecture enables real-time sound processing tailored to the user's specific auditory deficit.
If you are an implant developer dealing with suboptimal sound encoding for patients — this project developed FPGA processors that embed augmented-hearing sound processors. This improves the quality of sound delivered directly to the auditory nerve.
Based on available project data, the specific unit price or cost of the CochSyn device is not disclosed.
The project aims to transition from TRL4 to TRL5-6 by implementing the test in a portable medical device and developing FPGA hardware demonstrators for market entry.
The project explicitly aims to consolidate its IP portfolio and set out a business strategy for market entry in the hearable and hearing-aid sectors.
The CoNNear algorithm is designed as a sound processor that can be embedded into hearables, hearing aids, and cochlear implants via FPGA processors.
The project period runs from 2022-08-01 to 2026-01-31, with the goal of reaching TRL 5-6 by the end of the term.
The project is led solely by Universiteit Gent (Belgium), meaning it is currently a university-driven research effort with 0 industrial partners. While this indicates high scientific quality, the lack of industry partners in the consortium suggests the project is in the early stages of market transition, focusing on moving from TRL4 to TRL6.
Contact the research department at Universiteit Gent regarding the EarDiTech project.
Contact us to find licensing opportunities for the CoNNear algorithm.
