BeFerroSynaptic · Project

Brain-Inspired Computer Chips That Cut AI Energy Costs Dramatically

digitalPrototypeTRL 4Thin data (2/5)

Today's computers waste enormous energy moving data back and forth between where it's stored and where it's processed — like a chef running between a pantry in another building and the kitchen for every single ingredient. This project built tiny electronic devices made from special ferroelectric materials that can store and process information in the same spot, mimicking how brain cells (synapses) work. They stacked these devices directly on top of existing chip technology, proving that brain-like computing hardware can be manufactured using methods the semiconductor industry already knows. The result is a path toward AI chips that use a fraction of the energy current hardware requires.

By the numbers

consortium partners

countries in consortium

industrial partners (semiconductor sector)

total project deliverables

target TRL level (feasibility demonstration)

The business problem

What needed solving

Today's AI hardware burns massive amounts of energy because processors must constantly shuttle data between separate memory and computing units — the so-called von Neumann bottleneck. As AI workloads grow exponentially in data centers, edge devices, and autonomous systems, the electricity cost and thermal limits of conventional chip architectures are becoming a serious business constraint. Companies need fundamentally more efficient computing hardware to run AI affordably at scale.

The solution

What was built

The project built ferroelectric synaptic devices (FeFETs and FTJs) using hafnium-oxide-based materials integrated on top of existing CMOS chips. They delivered a demonstration of on-line learning and classification validated against standard benchmarks, along with 15 total deliverables covering the device technology, integration process, and neuromorphic processor design.

Audience

Who needs this

Semiconductor foundries looking to add neuromorphic AI capabilities to their product linesEdge AI hardware companies needing ultra-low-power inference chips for IoT and roboticsData center operators seeking to reduce electricity costs for AI workloadsAutomotive chip designers building energy-efficient processors for autonomous drivingDefense and aerospace electronics firms requiring AI processing in power-constrained environments

Business applications

Who can put this to work

Semiconductor Manufacturing

enterprise

Target: chip foundries and semiconductor design houses

If you are a semiconductor company dealing with the growing demand for energy-efficient AI chips — this project developed a ferroelectric device platform (FeFET and FTJ) that integrates directly on top of existing CMOS technology using back-end-of-line processes. That means you could add neuromorphic capabilities to your existing fabrication lines without building new fabs. The consortium included 2 industrial partners from the semiconductor sector and demonstrated feasibility at TRL 4.

Edge Computing & IoT

any

Target: companies building AI-powered edge devices and embedded systems

If you are an edge computing company struggling with power budgets for on-device AI — this project demonstrated on-line learning and classification on neuromorphic hardware that processes data where it is stored, eliminating the energy-hungry data shuttling of conventional processors. For battery-powered IoT sensors, wearables, or autonomous drones, this ferroelectric approach could extend operating time significantly. The technology was validated by a 13-partner consortium across 6 countries.

Data Centers & Cloud Computing

enterprise

Target: hyperscale data center operators and cloud AI service providers

If you are a data center operator facing rising electricity costs from AI workloads — this project tackled the von Neumann bottleneck that forces conventional processors to burn energy moving data between memory and compute units. The ferroelectric synaptic devices developed here merge memory and logic into single units, targeting a fundamentally more efficient architecture for neural network processing. The platform was built on industry-standard CMOS technology with 2 industrial partners involved.

Frequently asked

Quick answers

What would it cost to license or adopt this technology?

The project was a Research and Innovation Action targeting TRL 4 (feasibility demonstration), so there is no commercial product or published pricing yet. Licensing would need to be negotiated directly with the consortium, led by NaMLab gGmbH in Germany, which holds expertise in ferroelectric device integration. Any commercialization path would likely involve joint development agreements with a semiconductor foundry.

Can this scale to industrial semiconductor production?

The technology was specifically designed for back-end-of-line (BEOL) integration on top of existing CMOS technology, which is a major advantage for scalability. The consortium included 2 industrial partners from the semiconductor industry. However, at TRL 4, the feasibility was demonstrated but full manufacturing-scale integration has not yet been proven.

Who owns the intellectual property?

IP is shared among the 13 consortium partners according to their Horizon 2020 grant agreement. Key technology contributors include 5 research organizations and 4 universities. Businesses interested in licensing specific components would need to contact the coordinator (NaMLab gGmbH) to identify the relevant IP holders.

How does this compare to other neuromorphic chip approaches?

This project differentiates by using ferroelectric hafnium oxide (HfO2/HZO) materials, which are already compatible with standard semiconductor manufacturing, unlike exotic materials used in competing approaches. The BEOL integration strategy means the devices can be added on top of existing chip designs rather than requiring entirely new fabrication processes.

What was actually demonstrated and validated?

The project delivered a demonstration of on-line learning and classification, evaluated against standard and project-specific benchmarks. This validates that the ferroelectric synaptic devices can perform real AI tasks. A total of 15 deliverables were produced across the project's duration from 2020 to 2023.

What regulations or standards apply?

Semiconductor manufacturing follows established industry standards (e.g., JEDEC for memory reliability). Since the technology uses CMOS-compatible materials and processes, it falls within existing regulatory and qualification pathways. No novel materials requiring special regulatory approval are involved — HfO2 is already widely used in the semiconductor industry.

Consortium

Who built it

The BeFerroSynaptic consortium brings together 13 partners from 6 countries (Switzerland, Germany, Greece, France, Italy, Netherlands), with a strong academic backbone of 6 universities and 5 research organizations. The 2 industrial partners — notably including major semiconductor players X-FAB and IBM as mentioned in the project description — provide critical manufacturing and commercialization expertise, though the 15% industry ratio means this is primarily a research-driven effort. For a business considering this technology, the involvement of X-FAB (a leading specialty foundry) and IBM signals genuine industrial relevance, but the path from TRL 4 to a commercial product will require significant additional investment and partnership.

NAMLAB GGMBHCoordinator · DE
UNIVERSITA DEGLI STUDI DI UDINEthirdparty · IT
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESparticipant · FR
IBM RESEARCH GMBHparticipant · CH
X-FAB Dresden GmbH & Co. KGparticipant · DE
HELMHOLTZ-ZENTRUM BERLIN FUR MATERIALIEN UND ENERGIE GMBHparticipant · DE
EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZUERICHparticipant · CH
NATIONAL CENTER FOR SCIENTIFIC RESEARCH "DEMOKRITOS"participant · EL
UNIVERSITAT ZURICHparticipant · CH
CONSORZIO NAZIONALE INTERUNIVERSITARIO PER LA NANOELETTRONICAparticipant · IT
RIJKSUNIVERSITEIT GRONINGENparticipant · NL
UNIVERSITA DEGLI STUDI DI MODENA E REGGIO EMILIAthirdparty · IT
TECHNISCHE UNIVERSITAET DRESDENparticipant · DE

How to reach the team

NaMLab gGmbH is a research center in Dresden, Germany — a leading hub for semiconductor innovation. Contact them through their institutional website for technology licensing inquiries.

Order a report on this consortium See NAMLAB GGMBH profile →

Next steps

Talk to the team behind this work.

Want to explore whether ferroelectric neuromorphic technology fits your AI hardware roadmap? SciTransfer can arrange a targeted briefing with the research team and assess integration feasibility for your specific use case.

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