Imagine a light switch that requires almost zero effort to flip. Current computer chips have a physical 'floor' on how little energy they can use to switch on and off, which wastes a lot of power. This project uses special materials like graphene to break through that floor, making electronics that run on tiny fractions of the energy they use today.
Current CMOS transistors are limited by Boltzmann physics, creating a floor for operating voltage and power consumption. This prevents further energy efficiency gains as ICT energy demand threatens to hit 20% of global totals.
The project is building scalable Dirac transistors (DFET) using graphene and CoSi, supported by a multi-level simulation portfolio from atomistic to TCAD.
If you are a data center operator dealing with energy demands that could reach 20% of total global energy by the end of the decade — this project developed Dirac transistors that achieve a switching energy of 4 attojoule. This allows for massive reductions in cooling costs and electricity bills.
If you are a chip designer dealing with battery life limits in smartphones — this project developed a cold-source transistor technology that overcomes the Boltzmann limit. This enables devices to perform complex logic with significantly lower power draw.
If you are a hardware manufacturer dealing with heat dissipation in high-frequency analog chips — this project developed 2D and 3D Dirac material integration. This provides ultra-energy-efficient transistors for high-frequency analog integrated chip markets.
Based on available project data, there is no information regarding the unit cost or pricing of the developed transistors.
The project aims to develop a scalable technology based on large-area integration of 2D and 3D Dirac materials to ensure it is technologically relevant.
Based on available project data, specific licensing terms are not listed, though the project involves a consortium of 9 partners across 6 countries.
The project period runs from 2024-01-01 to 2027-06-30, suggesting a roadmap toward maturity by mid-2027.
The project focuses on developing device process modules and links to the 2D-experimental pilot line to align with the European Chips Act.
The consortium consists of 9 partners from 6 countries, showing a strong academic lean with 4 universities and 3 research organizations. However, the inclusion of 1 industry partner and 1 SME (11% industry ratio) indicates a bridge toward commercialization, coordinated by a national consortium for nanoelectronics in Italy.
Contact the Consorzio Nazionale Interuniversitario per la Nanoelettronica in Italy
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