3D-MUSE · Project

Stacking Chip Layers to Build Smarter, Smaller, Lower-Power IoT Sensors

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Imagine you could build a computer chip like a multi-story building instead of a sprawling single-floor warehouse. That's what 3D-MUSE did — they figured out how to stack analog sensor circuitry on top of digital processing circuitry in a single chip, using a two-tier 28nm manufacturing process. This means IoT sensor devices can pack more intelligence into a tiny space while sipping far less power — potentially running on energy harvested from their environment alone. The result is sensor chips that are cheaper, smaller, and smart enough to process data right where it's collected.

By the numbers

consortium partners

countries involved (FR, NO, SE)

industry partners in consortium

28nm

FDSOI technology node used for bottom tier

metal line levels in bottom tier

total project deliverables

tiers in 3D sequential integration architecture

The business problem

What needed solving

IoT devices need to pack more sensors and more processing power into ever-smaller packages while running on minimal power — ideally harvested from the environment. Current chip manufacturing forces engineers to choose between optimizing for analog sensor performance or digital processing efficiency, because both require different fabrication processes. This bottleneck limits how smart, small, and energy-efficient sensor nodes can be.

The solution

What was built

The project built a proof of concept for 3D sequential chip integration combining analog and digital circuits in a two-tier architecture using 28nm FDSOI technology. Key deliverables include the completed bottom-tier processing with 4 metal line levels and a full proof-of-concept demonstration of the smart sensor interface, across 11 total deliverables.

Audience

Who needs this

Semiconductor foundries exploring next-generation 3D chip integration processesIoT sensor module manufacturers needing ultra-low-power multi-sensor packagesWearable device companies constrained by chip size and battery lifeSmart building and smart city solution providers deploying large sensor networksAutomotive sensor companies designing compact in-vehicle sensing systems

Business applications

Who can put this to work

Semiconductor manufacturing

enterprise

Target: Chip foundries and fabless semiconductor companies designing IoT sensor chips

If you are a semiconductor company struggling to shrink mixed-signal sensor chips while keeping power consumption low — this project developed a two-tier sequential 3D integration process using 28nm FDSOI technology that stacks analog and digital circuits vertically. This lets you put specialized analog sensor interfaces on one tier and optimized digital processing on another, avoiding the usual compromises of single-process designs. The consortium delivered a working proof of concept with 7 partners across 3 countries.

Industrial IoT and smart factory systems

mid-size

Target: Companies building wireless sensor networks for factory monitoring and predictive maintenance

If you are an industrial IoT company that needs sensor nodes small and efficient enough to run on harvested energy — this project proved that 3D sequential chip integration can combine sensor interfaces and processing into ultra-compact packages. Their two-tier architecture means your sensor nodes could process data locally without needing large batteries or wired power. The technology was validated at proof-of-concept level with industry partners including STMicroelectronics-grade 28nm processing.

Consumer electronics and wearables

any

Target: Wearable device manufacturers needing multi-sensor integration

If you are a wearable electronics company struggling to fit multiple sensors plus processing into tiny form factors — this project demonstrated how to vertically integrate mixed-signal circuits so that analog sensors and digital brains share a single compact chip stack. Their approach targets exactly the bottleneck you face: combining many different sensors in one product without ballooning size, cost, or power draw. The proof of concept was realized using 11 deliverables across a 7-partner European consortium.

Frequently asked

Quick answers

What would it cost to license or adopt this 3D integration technology?

Based on available project data, specific licensing terms or cost figures are not disclosed. The technology was developed as part of a publicly funded Research and Innovation Action, so licensing would need to be negotiated with the University of Oslo as coordinator. Given the semiconductor-grade complexity (28nm FDSOI processing), adoption costs would likely involve significant foundry partnership investment.

Can this technology work at industrial manufacturing scale?

The project delivered a proof of concept using 28nm FDSOI technology processing, which is a mainstream industrial node. However, scaling from proof of concept to volume production would require further process qualification at a commercial foundry. The consortium included 2 industry partners, suggesting early industry involvement in scale-up considerations.

What is the IP situation — who owns the technology?

As an EU-funded RIA project, IP typically stays with the partners who generated it. The consortium of 7 partners across Norway, France, and Sweden likely holds different aspects of the IP. Specific patent filings are not detailed in the available data, so interested parties should contact the coordinator at the University of Oslo.

How does this compare to existing 3D chip stacking approaches?

The project explicitly distinguishes its 'systems-in-cube' approach from conventional 'systems-in-stack' methods that use wafer bonding. Their sequential 3D integration achieves much higher interconnect density between tiers, enabling functional blocks to span multiple layers rather than being confined to a single plane. This is a fundamentally different manufacturing approach from parallel 3D integration.

What was actually demonstrated and when?

The project ran from 2018 to 2022 and delivered 11 total deliverables including 2 key demonstrations: a 3D sequential integration smart sensor interface proof of concept, and completed 28nm FDSOI bottom-tier processing with 4 metal line levels. These confirm the core concept was physically realized in silicon.

Is this ready for commercial products today?

Based on available project data, the technology reached proof-of-concept stage — validated in a lab environment but not yet piloted in commercial products. The 28nm bottom tier was fabricated, and the two-tier integration concept was demonstrated. Further engineering and foundry qualification would be needed before this appears in commercial sensor chips.

What regulatory or standards considerations apply?

Based on available project data, no specific regulatory hurdles are mentioned. Standard semiconductor industry qualifications (reliability testing, process certification) would apply. IoT devices built with this technology would need to meet relevant wireless and safety standards depending on the application domain.

Consortium

Who built it

The 3D-MUSE consortium brings together 7 partners from 3 countries (France, Norway, Sweden), with a mix of 3 universities, 2 research organizations, and 2 industry partners (29% industry ratio), including 1 SME. The coordinator is the University of Oslo, a strong academic institution but not an industry player — meaning commercialization will depend on the industry partners driving adoption. The French and Scandinavian partnership suggests connections to major European semiconductor ecosystems. For a business looking to access this technology, the industry partners would be the most practical entry point, while the academic partners hold deep process knowledge.

UNIVERSITETET I OSLOCoordinator · NO
INSTITUT POLYTECHNIQUE DE GRENOBLEparticipant · FR
STMICROELECTRONICS CROLLES 2 SASparticipant · FR
LUNDS UNIVERSITETparticipant · SE
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESparticipant · FR
INTEGRATED DETECTOR ELECTRONICS ASparticipant · NO
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRSthirdparty · FR

How to reach the team

University of Oslo (Norway) — contact through CORDIS project page or university research office

Order a report on this consortium See UNIVERSITETET I OSLO profile →

Next steps

Talk to the team behind this work.

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