Imagine a computer memory chip that doesn't forget data when the power is cut, but uses almost no electricity to save or change information. Instead of using bulky magnets, this uses layers of materials so thin they are only a few atoms thick. It's like switching from a heavy mechanical light switch to a high-tech touch sensor for data storage.
Current non-volatile memory materials are inefficient, requiring high currents and magnetic fields to operate. This limits the speed, miniaturization, and energy efficiency of modern electronic devices.
The project developed all-2D SOT device units using 2D ferromagnets and spin-orbit materials. These prototypes demonstrate magnetization switching at room temperature without the need for external magnetic fields.
If you are a hardware manufacturer dealing with short battery life and heat issues — this project developed all-2D SOT devices that enable energy-efficient, fast, and non-volatile memory. This allows devices to retain information after shutdown while consuming minimal power.
If you are a chip designer dealing with the massive energy demands of AI processing — this project developed a 2D materials platform for memory in computing applications. This supports the high-speed data processing required for AI and edge computing.
If you are an IoT company dealing with the need for scalable, low-power data storage in remote sensors — this project developed 2D heterostructure memory that works at room temperature without magnetic fields. This enables scalable data storage and processing devices.
Based on available project data, there is no specific pricing or cost-per-unit mentioned; the project focuses on the research and prototype phase.
The project aims to move from basic research to prototype devices (TRL3-4), focusing on scalable data storage, though full industrial mass-production details are not provided.
Based on available project data, specific licensing terms are not listed, but the consortium includes a company in the field of spintronics and 2D materials.
The technology uses van der Waals heterostructures to create memory units that could potentially replace or augment current non-volatile memory in computing architectures.
The project period is from 2023-12-01 to 2027-05-31.
The consortium is heavily research-oriented, consisting of 7 partners from 5 countries, with 5 universities and 1 research institute. Industry participation is low at 14% (1 company), indicating that the project is currently in the early translation phase from lab to market, though it includes 2 SMEs to help bridge this gap.
Contact Chalmers Tekniska Hogskola AB in Sweden
Contact us to connect with the 2DSPIN-TECH consortium for early licensing discussions.
