Imagine trying to draw a map of a city on a grain of rice; that is the level of precision needed for the next generation of computer chips. This work focuses on making the 'brushes' and 'rulers' small and accurate enough to build these tiny circuits. It also finds ways to keep the machines cool and clean so they can run faster without wasting energy.
The semiconductor industry faces a physical limit in shrinking chip components while maintaining performance and energy efficiency. Current manufacturing processes struggle with overlay precision and high energy consumption during the EUV lithography process.
Developed a framework for projection optics dynamics, a time-resolved spectrometer for scanner conditions, and new amplifier boards for power efficiency. Also created a simulation-based mask repair strategy and ultra-high precision wafer stages.
If you are a device manufacturer dealing with the plateau of processing power — this project developed 14A technology nodes that enable smaller, faster, and more efficient chips. This allows for more advanced automation in mobility and health applications.
If you are an equipment maker dealing with high energy costs and heat management — this project developed a system to use cooling water at 32 °C instead of 20 °C. This reduces the carbon footprint of EUV-chips and improves power efficiency.
If you are a security firm dealing with the need for more complex on-chip encryption — this project developed 14A patterning and process solutions. This enables new high-security applications in communication and research.
Based on available project data, specific pricing or implementation costs are not provided, though the project aims to demonstrate a cost-efficient solution for the 14A node.
The project is designed to enable the IC industry to migrate to the next technology node, involving 20 industrial partners to ensure scalability.
Based on available project data, specific licensing terms are not mentioned, but the consortium includes major industry players like ASML and Carl Zeiss.
The project period runs from 2022-12-01 to 2026-05-31, with some components like the first POB expected in the second half of the current reporting year.
The project involves Cadence to manage the interface with the design community, ensuring the 14A process modules align with chip design requirements.
The consortium is heavily industry-driven, with an 80% industry ratio consisting of 20 companies and only 2 universities. Led by ASML, it includes a powerful network of 25 partners across 8 countries, combining the world's leading lithography, metrology, and process tool providers (e.g., Carl Zeiss, Trumpf, imec, TEL). This structure indicates a strong focus on commercial viability and direct integration into the semiconductor supply chain rather than pure academic research.
Contact ASML NETHERLANDS B.V. regarding 14A CMOS technology development
Contact us to identify licensing opportunities for 14A metrology and lithography tools.
