Imagine trying to draw a map of a city on a grain of sand; that is the level of precision needed for the next generation of computer chips. This work focuses on creating a new 3D structure for transistors, like stacking building blocks instead of laying them flat, to fit more power into a smaller space. It also improves the 'cameras' and 'printing tools' used to make these chips so they are faster and waste fewer materials.
Current chip manufacturing is hitting physical limits, making it harder to increase processing power without increasing heat and size. There is a critical need for new transistor architectures and more precise lithography to keep Moore's Law viable.
A functional monolithic CFET (mCFET) device and upgraded EUV lithography tool components. New computational lithography software and high-throughput wafer characterization methods were also developed.
If you are a device manufacturer dealing with battery drain and overheating — this project developed 3D mCFET architecture that improves power, performance, and area. This allows for smaller, more efficient chips in mobile devices.
If you are an equipment provider dealing with high machine downtime and waste — this project developed refurbished modules and sustainable EUV tool components. This increases the lifespan of expensive machinery and reduces production costs.
If you are a quality control firm dealing with slow wafer inspection speeds — this project developed high throughput and sample density analysis for 10Å devices. This allows for faster defect detection and higher yield during mass production.
Based on available project data, specific cost or pricing information for the 10Å technology is not provided.
The project involves 27 industry partners, including ASML and Intel, focusing on increasing yield and wafer throughput, which indicates a strong drive toward industrial scaling.
Based on available project data, the specific licensing terms are not mentioned, though the consortium includes major IP holders like ARM and imec.
The project period runs from 2024-05-01 to 2027-04-30, suggesting the exploration and realization phase concludes in early 2027.
The project includes Siemens and ARM to develop new computational lithography solutions and assess the impact of 3D mCFET on chip design.
The consortium is heavily weighted toward industrial application, with an 84% industry ratio comprising 27 companies. Led by ASML, it integrates the entire semiconductor value chain, from design (ARM, Siemens) and manufacturing (Intel, imec) to equipment (Applied Materials, KLA, TEL) and optics (Zeiss). This structure ensures that the research is directly aligned with commercial manufacturing requirements and equipment capabilities.
Contact ASML NETHERLANDS B.V. regarding EUV tool performance and 10Å node roadmaps.
Contact SciTransfer for a detailed analysis of the 3D mCFET supply chain.
